| Building Zero Latency Vector Multiplication Engines Using FPGAs, SAAHPC 2010 |
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| Nallatech In-Socket FPGA Front Side Bus Accelerator, Computing in Science and Engineering Volume 12 No.2. April 2010 |
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OpenFPGA CoreLib core library interoperability effort, Parallel Computing, Volume 34 , Issue 4-5, 2008.
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| Implementing Closed-Form Expressions on FPGAs Using the NAL, with Comparison to CUDA GPU and Cell BE Implementations, Reconfigurable Systems Summer Institute 2008 |
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| Restoration of Star-Field Images Using High-Level Languages and Core Libraries, Manchester Reconfigurable Supercomputing Conference (MRSC) 2007 |
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| Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C, AHS2007 Special Session on High-Performance Reconfigurable Computing |
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| Minimum Entropy Restoration Using FPGAs and High-Level Techniques, EUSIPCO 2007 |
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| An Elementary Transcendental Function Core Library for Reconfigurable Computing, RSSI 2007 |
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| OpenFPGA CoreLib Core Library Interoperability Effort, RSSI 2007 |
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| A Streaming FFT on 3GSPS ADC Data using Core Libraries and DIME-C, HPEC 2007 |
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Learning to Implement Floating-Point Algorithms on FPGAs Using High-Level Languages, International Workshop on Reconfigurable Computing Education 2006
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The LB model with Configurable Computing, International Supercomputer Conference (ISC2006)
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A study into implementing the Lattice Boltzmann floating point model with reconfigurable computing, Reconfigurable Systems Summer Institute (RSSI 2006)
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Implementing the VSIPL API on Reconfigurable Computers, Reconfigurable Systems Summer Institute 2006
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Lessons Learned Implementing the VSIPL API on Reconfigurable Computers, 9th Annual MAPLD Conference (MAPLD 2006)
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Implementing Algorithms on FPGAs Using High-Level Languages and Low-Level Libraries, International Conference for High Performance Computing, Networking, Storage and Analysis (Supercomputing - SC'06)
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A high throughput FPGA camellia implementation, Ph.D. Research In Micro-Electronics & Electronics (PRIME) 2005 - Best Paper Award
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High-Level Implementation of VSIPL on FPGA-based Reconfigurable Computers, Military and Aerospace Programmable Logic Devices (MAPLD) 2005
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| Implementation of Floating-Point VSIPL Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages, High Performance Embedded Computing 2005 |
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| Implementation of Floating-Point Vector Signal Image Processing Library Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages, ICSP Research Colloquium 2005 |
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| Hardware co-simulation in system generator of the AES-128 encryption algorithm, ACM/SIGDA 12th International Symposium on Field Programmeable Gate Arrays (FPGA 2004) |
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| Implementation of Floating-Point Vector Signal Image Processing Library Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages, ICSP Research Colloquium 2005 |
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| Accelerate and verify algorithms with the Xtreme DSP development Kit-II, Xcell Journal [Xilinx industry journal]. Issue 49 |
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| Multi-user FPGA, co-simulation over TCP/IP, Proceeding of 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004) |
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| Implementation of Floating-Point Vector Signal Image Processing Library Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages, ICSP Research Colloquium 2005 |
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| Implementation of Floating-Point Vector Signal Image Processing Library Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages, ICSP Research Colloquium 2005 |
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